In a vertical semiconductor device having a channel, such as a vertical metal oxide semiconductor field-effect transistor (MOSFET) and an insulated-gate bipolar transistor (IGBT), and in a structure generally called a planar type in which the channel is formed in a direction parallel to a main surface, in order to reduce channel resistance, a plane layout having high channel width density is desired.
As a method of forming the layout, for example, as disclosed in Patent Document 1 and Patent Document 2, forming channels in directions on two straight lines orthogonal to each other (hereinafter, grid arrangement) is widely known by making a well region a quadrangular cell shape in plan view and disposing the well region on a grid.